Method of fabricating non-volatile memory

ABSTRACT

A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 94106211, filed on Mar. 2, 2005. All disclosure of the Taiwanapplication is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating semiconductormemory device. More particularly, the present invention relates to amethod of fabricating non-volatile memory.

2. Description of the Related Art

Among the various types of non-volatile memory products, electricallyerasable programmable read only memory (EEPROM) is a memory device thathas been widely used inside personal computer systems and electronicequipment. In the EEPROM, data can be stored, read out or erasednumerous times and stored data are retained even after power is cut off.

Typically, the floating gate and the control gate of an EEPROM cell arefabricated using doped polysilicon. In the conventional technique, acharge-trapping layer is sometimes used to replace a floating gatefabricated from polysilicon material. The charge-trapping layer is, forexample, fabricated using silicon nitride. In general, an oxide layer isformed both above and below the silicon nitride charge-trapping layer toform an oxide-nitride-oxide (ONO) composite structure. This type ofmemory is often referred to as a silicon-oxide-nitride-oxide-silicon(SONOS) memory device.

The semiconductor manufacturers have produce one kind of non-volatilememory with a structure shown schematically in FIG. 1. The non-volatilememory includes a memory cell column having a plurality of first memorycells 102 and a plurality of second memory cells 116. The first memorycells 102 are separated from the second memory cells 116 throughinsulating spacers 110 respectively. Each first memory cell 102 includesa bottom dielectric layer 104 a, a charge-trapping layer 104 b, a topdielectric layer 104 c (the bottom dielectric layer 104 a, thecharge-trapping layer 104 b and the top dielectric layer 104 c togetherform a composite layer 104), a gate 106 and a cap layer 108 sequentiallystacked on the substrate 100. Each second memory cell 116 similarlyincludes a bottom dielectric layer 112 a, a charge-trapping layer 112 b,a top dielectric layer 112 c (the bottom dielectric layer 112 a, thecharge-trapping layer 112 b and the top dielectric layer 112 c togetherform a composite layer 112) and a gate 114 sequentially stacked on thesubstrate 100. Because there is no gap between neighboring memory cells,the level of integration of devices for this type of non-volatile memoryis increased.

However, the gates 106 of the first memory cells 102 are fabricated froma polycide material that includes a doped polysilicon layer 106 a and ametal silicide layer 106 b. On the other hand, the gates 114 of thesecond memory cells 116 are fabricated from a doped polysiliconmaterial. Since the doped polysilicon material has a resistance muchgreater than the polycide material, there is a significant difference inthe electrical performance between the first memory cells 102 and thesecond memory cells 116. Hence, there will be a drop in the electricalperformance of the devices and a greater instability in the deviceprocess.

SUMMARY OF THE INVENTION

Accordingly, at least one objective of the present invention is toprovide a method of fabricating a non-volatile memory that can reducegate resistance, increase memory cell conductivity and increase deviceperformance and stability.

At least a second objective of the present invention is to provide amethod of fabricating a non-volatile memory that can in crease deviceperformance. Furthermore, the fabricating method can simplify themanufacturing process and reduce the production cost.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a method of fabricating a non-volatile memory havingthe following steps. First, a substrate is provided. Then, a pluralityof first memory units is formed on the substrate with every twoadjoining first memory units are separated from each other by a gap.Each first memory unit includes a first composite layer, a first gateand a cap layer sequentially formed on the substrate. The firstcomposite layer includes a first dielectric layer, a firstcharge-trapping layer and a top dielectric layer, for example.Thereafter, a plurality of insulating spacers is formed on the sidewallsof the first memory units. After that, a second composite layer isformed over the substrate. The second composite layer includes a secondbottom dielectric layer, a second charge-trapping layer and a second topdielectric layer, for example. Then, a doped polysilicon layer is formedover the substrate to fill the gaps between various first memory units.A portion of the doped polysilicon layer is removed so that the surfaceof the doped polysilicon layer is at least lower than the top surface ofthe cap layer and a plurality of trenches is formed between the variousfirst memory units. A metallic layer is formed over the substrate tofill the trenches. Afterwards, a portion of the metallic layer isremoved until the second composite layer is exposed. The metallic layerand the doped polysilicon layer together form a plurality of secondgates, and the second gates and the second composite layer together forma plurality of second memory units. The second memory units and thefirst memory units together constitute a memory cell column. Thereafter,a source region and a drain region are formed on the two sides of thememory cell column.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, before thestep of forming the metallic layer on the substrate to fill thetrenches, further includes forming a barrier layer over the substrate.The barrier layer is a titanium/titanium nitride layer formed bysputtering, for example.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, themetallic layer is fabricated using tungsten or metal silicide compound.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, the methodof forming a metallic layer to fill the trenches on the substrateincludes performing a sputtering process or chemical vapor depositionprocess.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, the methodof removing a portion of the doped polysilicon layer and removing aportion of the metallic layer includes performing an etching backprocess.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, the firstbottom dielectric layer, the first top dielectric layer, the secondbottom dielectric layer, the second top dielectric layer can befabricated by silicon oxide and the first charge-trapping layer and thesecond charge-trapping layer can be fabricated by silicon nitride ordoped polysilicon, for example.

The present invention also provides an alternative method of fabricatinga non-volatile memory including the following steps. First, a substrateis provided. Then, a plurality of first memory units is formed on thesubstrate with every two adjoining first memory units are separated fromeach other by a gap. Each first memory unit includes a first compositelayer, a first gate and a cap layer sequentially formed on thesubstrate. The first composite layer includes a first bottom dielectriclayer, a first charge-trapping layer and a first top dielectric layer,for example. Thereafter, a plurality of insulating spacers is formed onthe sidewalls of the first memory units and then a second compositelayer is formed over the substrate. The second composite layer includesa second bottom dielectric layer, a second charge-trapping layer and asecond top dielectric layer, for example. After that, a dopedpolysilicon layer is formed over the substrate to fill the gaps betweenvarious first memory units. Then, a portion of the doped polysiliconlayer is removed so that the top surface of the doped polysilicon layeris at least below the top surface of the cap layer. Thereafter, a metalsilicide layer is formed over the doped polysilicon layer. The metalsilicide layer and the doped polysilicon layer together form a pluralityof second gates and the second gates and the second composite layertogether form a plurality of second memory units. The second memoryunits and the first memory units together constitute a memory cellcolumn. Then, a source region and a drain region are formed in thesubstrate on the two sides adjacent to the memory cell column.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, the methodof removing a portion of the doped polysilicon layer includes performingan etching back process.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, the methodof forming the metal silicide layer over the doped polysilicon layerincludes depositing metallic material to form a metallic layer over thesubstrate. Then, an annealing process is performed so that a portion ofthe metallic layer and the doped polysilicon layer react to form a metalsilicide layer. Thereafter, the metallic layer not participated in thereaction is removed. The metallic layer is fabricated using a refractorymetal such as cobalt or titanium and formed by sputtering, for example.

According to the aforementioned method of fabricating the non-volatilememory in the preferred embodiment of the present invention, the firstbottom dielectric layer, the first top dielectric layer, the secondbottom dielectric layer and the second top dielectric layer can befabricated by silicon oxide and the first charge-trapping layer and thesecond charge-trapping layer can be fabricated by silicon nitride ordoped polysilicon, for example.

In the method of fabricating the non-volatile memory according to thepresent invention, only one photomask is required to define the firstmemory units and the second memory cells is fabricated without using theconventional photolithographic and etching processes. Therefore, theprocessing is simplified and the production cost is reduced.Furthermore, using polycide compound to form the gate of the secondmemory units significantly reduces the gate resistance of the secondmemory units so that the second memory units can have greaterconductivity. The first memory units and the second memory units areelectrically comparable. Consequently, the performance and stability ofthe devices are improved.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view showing the structure of aconventional non-volatile memory.

FIGS. 2A through 2G are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to one preferredembodiment of the present invention.

FIGS. 2H through 2I are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to anotherpreferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIGS. 2A through 2G are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to one preferredembodiment of the present invention. As shown in FIG. 2A, a substrate200 is provided. Then, a plurality of memory units 207 is formed on thesubstrate 200 with every two adjoining first memory units 207 areseparated from each other by a gap 208. Each memory unit 207 includes acomposite layer 201, a gate 203 and a cap layer 205, for example. Themethod of forming the memory units 207 includes forming a compositedielectric material layer, a gate material layer and an insulatingmaterial layer sequentially over the substrate 100 and patterning theaforementioned material layers by performing photolithographic andetching processes.

The composite layer 201 includes a bottom dielectric layer 201 a, acharge-trapping layer 201 b and a top dielectric layer 201 c, forexample. The bottom dielectric layer 201 a is a silicon oxide layerformed, for example, by performing a thermal oxidation process. Thecharge-trapping layer 201 b is a silicon nitride layer formed, forexample, by performing a chemical vapor deposition process. The topdielectric layer 201 c is a silicon oxide layer formed, for example, byperforming a chemical vapor deposition process. Obviously, the bottomdielectric layer 201 a and the top dielectric layer 201 c can befabricated from other types of similar materials. Similarly, thematerial constituting the charge-trapping layer 201 b is not limited tosilicon nitride. Other types of material that can trap electric charges,for example, tantalum oxide, titanium-strontium acid, hafnium oxide ordoped polysilicon can be used as well.

The gates 203 can be fabricated by polycide material, for example. Themethod of forming the polycide layer includes forming a dopedpolysilicon layer 203 a over the substrate 200 and then forming a metalsilicide layer 203 b over the doped polysilicon layer 203 a. The metalsilicide layer 203 b is formed, for example, by performing a chemicalvapor deposition process or a self-aligned silicide process. The caplayer 205 is a silicon oxide layer formed, for example, by performing achemical vapor deposition process.

As shown in FIG. 2B, a plurality of insulating spacers 209 is formed onthe sidewalls of the memory units 207. The insulating spacers 208 arefabricated by silicon nitride or silicon oxide, for example. Theinsulating spacers 208 are formed, for example, by depositing insulatingmaterial over the substrate 200 to form an insulating material layer andthen performing an anisotropic etching process so that only a portion ofthe insulation material layer remains on the sidewalls of the memoryunits 207.

As shown in FIG. 2C, a composite layer 211 is formed over the substrate200. The composite layer includes a bottom dielectric layer 211 a, acharge-trapping layer 211 b and a top dielectric layer 211 c, forexample. The bottom dielectric layer 211 a is a silicon oxide layerformed, for example, by performing a thermal oxidation process. Thecharge-trapping layer 211 b is a silicon nitride layer formed, forexample, by performing a chemical vapor deposition process. The topdielectric layer 211 c is a silicon oxide layer formed, for example, byperforming a chemical vapor deposition process. Obviously, the bottomdielectric layer 211 a and the top dielectric layer 211 c can befabricated from other types of similar materials. Similarly, thematerial constituting the charge-trapping layer 211 b is not limited tosilicon nitride. Other types of material that can trap charges, forexample, tantalum oxide, titanium-strontium acid, hafnium oxide or dopedpolysilicon can be used as well.

As shown in FIG. 2D, a doped polysilicon layer 213 is formed over thesubstrate 200 to fill the gaps 208 between various memory units 207. Thedoped polysilicon layer 213 is formed, for example, by depositing anundoped polysilicon layer in a chemical vapor deposition and performingan ion implanting process thereafter.

As shown in FIG. 2E, a portion of the doped polysilicon layer 213 isremoved to form a plurality of trenches 215 between the memory units207. The top surface of the doped polysilicon layer 213 a is at leastlower than the top surface of the cap layer 205. The method of removinga portion of the doped polysilicon layer 213 includes performing anetching back process, for example. The depth of the trenches 215 can becontrolled through adjusting the time of the etching back process.

As shown in FIG. 2F, a metallic layer 217 is formed over the substrate200 to fill the trenches 215. The metallic layer 217 is a tungsten layerformed by sputtering, for example. However, the metallic layer 217 canbe fabricated by metal silicide such as tungsten metal silicide in achemical vapor deposition process. Furthermore, a material may bedeposited over the substrate 200 to form an additional barrier layer 216before forming the metallic layer 217 over the substrate 200 to fill thetrenches 215. The barrier layer 216 can be a titanium/titanium nitridelayer formed by sputtering, for example.

As shown in FIG. 2G, a portion of the metallic layer 217 is removeduntil the composite layer 211 is exposed. The method of removing aportion of the metallic layer 217 includes performing an etching backprocess, a chemical-mechanical polishing or some other suitable process.If the embodiment of the present invention includes forming a barrierlayer 216, a portion of the barrier layer 216 is removed while removinga portion of the metallic layer 217 to expose the composite layer 211.The metallic layer 217 a together with the doped polysilicon layer 213 aform a gate 219, and the gate 219 together with the composite layer 211form a memory unit 221. The memory units 211 and the memory units 207together constitute a memory cell column. Thereafter, any residual gatematerial 219 in the area designated for forming the source region andthe drain region on each side of the memory cell column is removed. Themethod of removing residual gate material 219 includes performing anetching process, for example. After that, a source region 231 a and adrain region 231 b are formed in the substrate on the two sides adjacentto the memory cell column. The step of forming the source region 231 aand the drain region 231 b includes implanting p-type ions or n-typeions, according to the actual desired device state, into the substratein an ion implant process, for example.

In the aforementioned embodiment, the gate 219 includes the metalliclayer 217 a and the doped polysilicon layer 213 a. Since the metalliclayer 217 a can be a tungsten layer or a metal silicide layer, theelectrical resistance of the gate 219 is significantly reduced.Furthermore, by forming a barrier layer over the doped polysilicon layer213 a, the ohmic contact with the doped polysilicon layer 213 a isimproved. In addition, the adhesive strength between the metallic layer217 a and the doped polysilicon layer 213 a is reinforced to bring downthe gate resistance so that the gate 219 can have a higher electricalconductivity. Thus, the electrical property of the gates 219 and thegates 203 is more compatible with each other and the performance of thedevices is improved.

FIGS. 2H through 2I are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to anotherpreferred embodiment of the present invention. FIG. 2H is a continuationfrom FIG. 2D. A portion of the doped polysilicon layer 213 is removed sothat the top surface of the doped polysilicon layer 213 b is at leastlower than the top surface of the cap layer 205. The step of removing aportion of the doped polysilicon layer 213 includes performing anetching back process.

As shown in FIG. 2I, a metal silicide layer 241 is formed over the dopedpolysilicon layer 213 b. The method of forming the metal silicide layer241 includes performing a self-aligned metal silicide process includingthe following steps. First, a metallic layer (not shown) made from arefractory metal such as cobalt or titanium is formed over the substrate200, for example, by sputtering. Thereafter, a thermal process isperformed so that a portion of the metallic layer reacts with the dopedpolysilicon layer 213 b to form the metal silicide layer 241. Afterthat, the metallic material in the metallic layer not participated inthe reaction is removed.

The metal silicide layers 241 together with the doped polysilicon layers213 b form a plurality of gates 243, and the gates 243 together with thecomposite layer 211 form a plurality of memory units 245. The memoryunits 245 and the memory units 207 together constitute a memory cellcolumn. Thereafter, any residual gate material 243 in the areadesignated for forming the source region and the drain region on eachside of the memory cell column is removed. The method of removingresidual gate material 243 includes performing an etching process, forexample. After that, a source region 247 a and a drain region 247 b areformed in the substrate 200 on the two sides adjacent to the memory cellcolumn. The step of forming the source region 247 a and the drain region247 b includes implanting p-type ions or n-type ions, according to theactual desired device state, into the substrate in an ion implantprocess, for example.

In the aforementioned embodiment, the gate 243 includes the metalsilicide layer 241 and the doped polysilicon layer 213 b. Hence, theresistance of the gate 243 is reduced. In addition, the metal silicidelayer 241 is formed in a self-aligned metal silicide process. Therefore,no additional photomask is required. Consequently, the process forforming the non-volatile memory is simplified and the production cost isreduced.

In summary, the gate of the memory unit in the method of fabricating thenon-volatile memory according to the present invention includes thedoped polysilicon layer 213 a and the metallic layer 217 a as shown inFIG. 2G. Alternatively, the gate of the memory unit includes the dopedpolysilicon layer 213 b and the metal silicide layer 241 as shown inFIG. 2I. Since only a single photomask is required to define the memoryunits 207 and there is no need to perform photolithographic and etchingprocesses to fabricate the gate of another memory unit, the processingis simplified and the production cost is reduced.

Moreover, the gate of the memory unit is a composite layer including adoped polysilicon layer together with a metallic layer or a metalsilicide layer. Hence, the gate resistance is reduced and gateconductivity is increased so that the electrical properties of thememory units 245 and the memory units 207 are compatible with eachother. Ultimately, the device performance and stability is improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A method of fabricating a non-volatile memory, comprising the stepsof: providing a substrate; forming a plurality of first memory units anthe substrate, wherein every two adjoining first memory units areseparated from each other by a gap, and each first memory unit comprisesa first composite layer, a first gate and a cap layer sequentiallystacked on the substrate and the first composite layer comprises a firstbottom dielectric layer, a first charge-trapping layer and a first topdielectric layer; forming a plurality of insulating spacers on thesidewalls of the first memory units; forming a second composite layerover the substrate, wherein the second composite layer comprises asecond bottom dielectric layer, a second charge-trapping layer and asecond top dielectric layer; forming a doped polysilicon layer over thesubstrate, wherein the doped polysilicon layer fills the gaps betweenvarious first memory units; removing a portion of the doped polysiliconlayer so that the top surface of the doped polysilicon layer is at leastlower than the top surface of the cap layer to form a plurality oftrenches between the first memory units; forming a metallic layer overthe substrate to fill the trenches; removing a portion of the metalliclayer until the second composite layer is exposed, wherein the metalliclayer together with the doped polysilicon layer form a plurality ofsecond gates, the second gates together with the second composite layerform a plurality of second memory units, and the second memory unitstogether with the first memory units constitute a memory cell column;and forming a source region and a drain region in the substrate on thetwo sides of the memory cell column.
 2. The method of claim 1, whereinbefore forming the metallic layer on the substrate to fill the trenches,further comprises a step of forming a barrier layer on the substrate. 3.The method of claim 2, wherein the material constituting the barrierlayer comprises titanium/titanium nitride.
 4. The method of claim 2,wherein the step of forming the barrier layer over the substratecomprises performing a sputtering process.
 5. The method of claim 1,wherein the material constituting the metallic layer comprises tungsten.6. The method of claim 5, wherein the step of filling the trenches withthe metallic layer comprises performing a sputtering process.
 7. Themethod of claim 1, wherein the material constituting the metallic layercomprises a metal silicide.
 8. The method of claim 7, wherein the stepof filling the trenches with the metallic layer comprises performing achemical vapor deposition process.
 9. The method of claim 1, wherein thestep of removing a portion of the doped polysilicon layer comprisesperforming an etching back process.
 10. The method of claim 1, whereinthe step of removing a portion of the metallic layer comprisesperforming an etching back process.
 11. The method of claim 1, whereinthe material constituting the first bottom dielectric layer, the firsttop dielectric layer, the second bottom dielectric layer and the secondtop dielectric layer comprises silicon oxide.
 12. The method of claim 1,wherein the material constituting the first charge-trapping layer andthe second charge-trapping layer comprises silicon nitride or dopedpolysilicon.